Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP3571497
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To contrive to provide subword decoders in each column block, which drives a sensing amplifier, without augmenting the area of a chip, by a method wherein a semiconductor memory comprises the subword decoders to make a subword selection only to subword lines on a memory cell region provided in each column block. SOLUTION: When subword decoders 14 to 17 are selected, main word lines 18 are connected with subword lines 19. Accordingly, in one main word line selected by a main word decoder 11, the one subword line 19 selected by a subword decoder selection circuit 12 is raised to a high state only to column blocks selected by column block selection lines 21. As a result, a hierarchical word selection in each column block becomes possible and as the subword decoders are provided on both sides of a memory cell region in each column block, the number of contacts, which are arranged in the directions intersecting orthogonally the word lines, is decreased and an augmentation in a chip size can be avoided.
Inventors:
Fujieda Kazuichiro
Application Number:
JP16461997A
Publication Date:
September 29, 2004
Filing Date:
June 20, 1997
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/41; G11C11/401; G11C11/407; H01L27/10; (IPC1-7): H01L27/10; G11C11/407; G11C11/41
Domestic Patent References:
| JP9045870A | ||||
| JP9035475A | ||||
| JP8340089A | ||||
| JP8139291A | ||||
| JP8102529A | ||||
| JP6195966A |
Attorney, Agent or Firm:
Tadahiko Ito