Title:
固体撮像装置
Document Type and Number:
Japanese Patent JP3576073
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a chip size by reducing the number of memory elements or the number of output signal lines after A/D conversion in a CMOS image sensor on which parallel A/D converters are mounted. SOLUTION: The output signals of pixels 121 and 122-12m are converted into 10 bit digital signals by A/D converters 111 and 112-11m, and inputted to D/A converters 211-213 as one column three pairs of three bits, three bits, and four bits respectively from the upper rank, and multi-level analog signal voltages including information for plural bits are outputted. The A/D converters 112-11m output the multi-level analog signals in the same way. Thus, it is possible to transmit 10 bit information only by three output signal lines 181-183, and to sharply reduce the wiring area of a chip. Also, the number of memories for preserving video signal output period values can be reduced so as to be enough to hold the values D/A converted by the D/A converters 211-213, and the miniaturization of the chip can be realized.
Inventors:
Tadashi Sugiki
Application Number:
JP2000191492A
Publication Date:
October 13, 2004
Filing Date:
June 26, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/146; H03M1/12; H04N5/335; H04N5/374; H04N5/376; H04N5/378; (IPC1-7): H04N5/335; H01L27/146
Domestic Patent References:
| JP9238286A | ||||
| JP9247494A | ||||
| JP200032350A |
Attorney, Agent or Firm:
Saichi Suyama