DCT演算装置 - Matsushita Electric Industrial Co., Ltd

Title:

DCT演算装置

Document Type and Number:

Japanese Patent JP3586427

Kind Code:

B2

Abstract:

There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit (102) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit (103) for subjecting the output data of the bit slice circuit (102) to butterfly operation; a ROM address generation circuit (104) for generating continuous ROM addresses; an RAC (105) for reading the data corresponding to the ROM addresses from ROMs (ROM0 SIMILAR ROM7) and accumulating the data by accumulation circuits (51a SIMILAR 51h); and a second butterfly operation circuit 106 for subjecting the output data of the RAC 105 to butterfly operation.

Inventors:

Masahiro Ohashi
Takeshi Nakamura

Application Number:

JP2000588974A

Publication Date:

November 10, 2004

Filing Date:

December 14, 1999

Export Citation:

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