Title:
半導体装置の保護素子
Document Type and Number:
Japanese Patent JP3590706
Kind Code:
B2
Abstract:
A protection device for protecting a semiconductor circuit from positive and negative overvoltage such as static electrical discharges. A p-type substrate is provided having a pair of spaced apart n-type regions formed therein. Each of the spaced apart n-type regions has a p+ region and an n+ region formed therein. Each of the spaced apart n-type regions also includes an n+ drain tap which has a portion in contact with the substrate. The n+ region and one p+ region of one of the spaced apart n-type regions are connected to a terminal of a semiconductor circuit. The n+ region and p+ regions of the other n-type region are connected to a power voltage of the semiconductor device. A insulated gate is formed on a p-type semiconductor substrate, and is in contact with both n+ drain taps. The gate is grounded. The bilateral protection device of the present invention protects the semiconductor circuit against positive and negative overvoltages.
Inventors:
Kanazawa University
Application Number:
JP35082996A
Publication Date:
November 17, 2004
Filing Date:
December 27, 1996
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L27/04; H01L21/822; H01L27/02; H01L27/06; (IPC1-7): H01L21/822; H01L27/04; H01L27/06
Domestic Patent References:
| JP6132485A |
Attorney, Agent or Firm:
Yukio Ono