Title:
高速桁上げのためのロジック構造および回路
Document Type and Number:
Japanese Patent JP3594601
Kind Code:
B2
Abstract:
Programmable logic devices which include multiple blocks of combinational function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bit is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides a dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.
Inventors:
New, Bernard Jay.
Application Number:
JP50826095A
Publication Date:
December 02, 2004
Filing Date:
August 31, 1994
Export Citation:
Assignee:
The Links, Inc.
International Classes:
G06F7/50; G06F7/503; G06F7/506; H03K19/173; H03K19/177; (IPC1-7): G06F7/50; H03K19/177
Domestic Patent References:
| JP4242825A | ||||
| JP3132212A | ||||
| JP6295233A | ||||
| JP6044049A |
Attorney, Agent or Firm:
Shin Uchihara