Title:
プログラマブルRAS/CAS発生回路
Document Type and Number:
Japanese Patent JP3595942
Kind Code:
B2
Abstract:
A circuit which increases the speed margin and reduces the circuit size of a programmable RAS/CAS generation circuit. At the beginning of the third cycle {3} in execution cycle (EX), reset signal (reset) is provided to 2-bit counter 52 along with count enable signal (cntenable) and CAS start signal (casstart). In the case of the 0 wait mode, 2-bit counter 52 is operated with count loop (0) and continues to output count value (0). Control signal generating circuit 54 makes CAS-active initially midway through the cycle (third cycle {3} during which the count output from 2-bit counter 52 has started and decodes (monitors) the count output (decode0,1,2) from 2-bit counter 52 thereafter with wait count set data (0wait-3wait) as a parameter. In this case, the value of count output (decode0,1,2) is as is at (0), so control signal generating circuit 54 generates CAS- of the same phase (namely, first transition and last transition occur at the same timing) by synchronizing it with system clock pulse (CLOCK).
Inventors:
Seiji Yanagita
Application Number:
JP29898794A
Publication Date:
December 02, 2004
Filing Date:
November 07, 1994
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
International Classes:
G06F12/02; G06F13/16; G11C8/18; (IPC1-7): G06F12/02
Domestic Patent References:
| JP5061761A | ||||
| JP6202934A | ||||
| JP6222975A | ||||
| JP6149652A |
Attorney, Agent or Firm:
Filial piety Sasaki