Title:
非同期パケットデータ多重化回路
Document Type and Number:
Japanese Patent JP3602042
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an asynchronous packet data multiplexer circuit that can reduce the number of components by writing input data to one memory in time division in the case of multiplexing asynchronous packet data received through channels. SOLUTION: Asynchronous data are subjected to re-timing by an internal clock and a multiplexed write CH selection signal corresponding to each of channels(CH) is periodically outputted at a rate at which data at a maximum rate can be selected. The data are written in a memory area of each CH under the condition that the CH of a write ready signal generated from the head of the data of each CH and the CH of a selection signal 345 are coincident. In the case of reading the data, a read control section 60 periodically generates a multiplexed read CH selection signal that takes status information with respect to the memory write given from a write control section 40 into account similarly to above. The data are sequentially read from an area corresponding to the CH under the condition that the CH of a read CH selection signal and a read ready signal generated on the basis of the detection of the tail end of retiming data of each CH are coincident.
Inventors:
Isao Kanaoka
Application Number:
JP2000281287A
Publication Date:
December 15, 2004
Filing Date:
September 18, 2000
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
H04J3/04; H04L47/43; H04L49/901; (IPC1-7): H04L12/56; H04J3/04
Domestic Patent References:
| JP4196654A | ||||
| JP3024844A | ||||
| JP7321819A |
Attorney, Agent or Firm:
Masahiko Desk
Kawai Nobuaki
Yasuhisa Tanizawa
Kawai Nobuaki
Yasuhisa Tanizawa