Title:
スキャンテスト回路
Document Type and Number:
Japanese Patent JP3606525
Kind Code:
B2
Abstract:
A scan test circuit includes a scan flip-flop that receives a reset signal, a data signal, a scan data signal, and a scan shift enable signal selecting either the data signal or the scan data signal. A reset control circuit controls the reset signal according to the scan shift enable signal. Even if the reset signal originates in a combinatorial circuit, the reset control circuit can prevent the flip-flop from being reset during a scan shift sequence, without the need for external control of the reset signal. Further control of the reset signal can be provided by a mask circuit. These reset control features enable improved fault coverage to be obtained with a reduced number of external input terminals, a reduced number of test patterns, and only a small amount of additional test circuitry.
Inventors:
Kenichi Natsume
Application Number:
JP2002353702A
Publication Date:
January 05, 2005
Filing Date:
December 05, 2002
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G01R31/317; G01R31/28; G01R31/3185; H01L21/822; H01L27/04; (IPC1-7): G01R31/28
Domestic Patent References:
| JP59142481A | ||||
| JP2001196539A |
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Koji Hagiwara
Tetsuo Kanamoto
Koji Hagiwara