Title:
ダイナミック型半導体記憶装置
Document Type and Number:
Japanese Patent JP3612276
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to provide a DRAM with high speed. SOLUTION: Each NMOS transistor 5 for deriving an NMOS sense amplifier is provided dispersedly at a cross part of a word-line snap region 2 and an NMOS sense amplifier region 3. At the same time, each PMOS transistor 6 for driving a PMOS sense amplifier is provided dispersedly at a cross part of the word-line snap region 2 and a PMOS sense amplifier region 4. In this case, source power supplies 7 and 8 in contact with each source of the driving NMOS transistor 5 and the PMOS transistor 6 are disposed in the same direction as the bit line, so the access time as well as the cycle time can be shortened.
Inventors:
Daisaburo Takashima
Yukito Owaki
Kenji Tsuchida
Yukito Owaki
Kenji Tsuchida
Application Number:
JP2000393531A
Publication Date:
January 19, 2005
Filing Date:
December 25, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/409; G11C11/401; H01L21/8242; H01L27/108; (IPC1-7): H01L21/8242; G11C11/401; G11C11/409; H01L27/108
Domestic Patent References:
| JP4212454A | ||||
| JP3016082A | ||||
| JP3091189A | ||||
| JP3283089A | ||||
| JP2053289A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai