Title:
JTAGを用いたI/Oトグル試験方法及び装置
Document Type and Number:
Japanese Patent JP3612336
Kind Code:
B2
Abstract:
A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. The test pattern of alternating data bits is then latched to the JTAG data latch register and driven onto the output pins of the IC chip. The bidirectional buffers connected to the output pins are then enabled for output while the IC tester tri-states its alternating data test pattern. The test pattern is then shifted by one bit within the IC's JTAG shift register and parallel loaded into the JTAG latch register on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip. The process is then repeated once more to provide an alternating transition for each of the output pins so that a toggle from high to low and also from low to high is satisfied for each of the output pins on the IC chip.
Inventors:
Mote, Elle, Rundle, Jr.
Application Number:
JP52797397A
Publication Date:
January 19, 2005
Filing Date:
September 26, 1996
Export Citation:
Assignee:
Samsung Electronics Company, Limited
International Classes:
G01R31/28; G01R31/3185; (IPC1-7): G01R31/28
Domestic Patent References:
| JP2181676A | ||||
| JP6213972A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu