Title:
メモリデバイス
Document Type and Number:
Japanese Patent JP3625688
Kind Code:
B2
Abstract:
It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.
Inventors:
Kikutake Yo
Masato Matsumiya
Satoshi Eto
Kuninori Kawabata
Masato Matsumiya
Satoshi Eto
Kuninori Kawabata
Application Number:
JP12428499A
Publication Date:
March 02, 2005
Filing Date:
April 30, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C7/10; G11C11/401; G11C11/409; G11C11/407; (IPC1-7): G11C11/409; G11C11/407
Domestic Patent References:
| JP10055674A | ||||
| JP7312080A | ||||
| JP7334985A | ||||
| JP7182854A | ||||
| JP10055670A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku