Title:
論理回路、論理回路の合成方法、半導体装置の製造方法及び半導体集積回路装置
Document Type and Number:
Japanese Patent JP3625973
Kind Code:
B2
Abstract:
The present invention provides a logic circuit by combining the pass transistor logic circuits and CMOS logic circuits to have excellent performance on circuit characteristic such as the area, delay time and power consumption; a binary decision diagram is made from logic functions, each node of it is converted to a pass transistor selector with 2 inputs, 1 outputs and 1 control input to synthesize a pass transistor logic circuit; and, in the pass transistor logic circuit, one input of the two inputs other than the control signal input is fixed at logical constant ""1"" or ""0"" and used as a pass transistor selector with NAND logic or NOR logic operations and is changed into an equivalent CMOS gate such as NAND or NOR; and, if changed into CMOS gates, the predetermined value of electrical characteristic will be closer to the optimized value (for example, the area, the delay time or the power consumption will be smaller) so as to change the pass transistor selector into CMOS gate.
Inventors:
Yamashita Haruzo
Kazuo Yano
Kazuo Yano
Application Number:
JP54897A
Publication Date:
March 02, 2005
Filing Date:
January 07, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/82; G06F17/50; H03K19/0948; H03K19/173; (IPC1-7): H03K19/173; H01L21/82; H03K19/0948
Domestic Patent References:
| JP1256219A | ||||
| JP1129611A | ||||
| JP7168874A | ||||
| JP7202680A | ||||
| JP9006821A | ||||
| JP8313597A | ||||
| JP8007571A | ||||
| JP1216622A | ||||
| JP4230521A |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka
Yasuo Sakuta
Yasuo Sakuta