Title:
マイクロプロセッサシステム
Document Type and Number:
Japanese Patent JP3644959
Kind Code:
B2
Abstract:
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
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Inventors:
Center cheryl
Wang Johannes
Wang Johannes
Application Number:
JP50906394A
Publication Date:
May 11, 2005
Filing Date:
September 03, 1993
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G06F9/30; G06F12/08; G06F9/312; G06F9/318; G06F9/34; G06F9/38; G06F12/00; (IPC1-7): G06F9/38
Domestic Patent References:
| JP2148238A | ||||
| JP477925A | ||||
| JP58217054A | ||||
| JP6436336A |
Other References:
Mike Johnson,「Superscalar MicroprocessoR Design」,Prentice Hall,Englewood Cliffs,New Jersey,1991年発行,PP.50-53,PP.147~163
Attorney, Agent or Firm:
Meisei International Patent Office
Hirukawa Masanobu
Ryukichi Abe
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa
Hirukawa Masanobu
Ryukichi Abe
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa