Title:
半導体メモリ装置のキャパシタ下部電極の製造方法
Document Type and Number:
Japanese Patent JP3741518
Kind Code:
B2
Abstract:
An electrode structure is fabricated on a microelectronic substrate by forming an amorphous silicon electrode on the microelectronic substrate and cleaning the surface of the amorphous silicon electrode to remove contaminants and surface oxides therefrom. A thin amorphous silicon layer is formed on the clean surface of the amorphous silicon electrode. Silicon crystal nuclei are then formed and grown on the thin amorphous silicon layer. The electrode structure may be used as a bottom electrode for an integrated circuit capacitor, such as the storage capacitor for an integrated circuit DRAM.
Inventors:
Minami Noboru
Kim
Park Swim Asahi
Kim
Park Swim Asahi
Application Number:
JP14303497A
Publication Date:
February 01, 2006
Filing Date:
May 16, 1997
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L27/108; H01L29/41; H01L21/02; H01L21/8242
Domestic Patent References:
| JP7130875A | ||||
| JP6151753A | ||||
| JP6163850A |
Attorney, Agent or Firm:
Masaki Hattori