半導体集積回路装置

Japanese Patent JP3781270

B2

A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

JPH03255663	MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE
JPS62200758	SEMICONDUCTOR MEMORY
JPH04134856	MANUFACTURE OF SEMICONDUCTOR DEVICE

Kiyoshi Ito
Kazuo Nakazato

JP2000619033A

May 31, 2006

May 14, 1999

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株式会社日立製作所

H01L27/108; G11C11/402; G11C11/405; G11C11/4076; H01L21/8242

JPH01255269A	1989-10-12
JPS6319847A	1988-01-27
JPH08250673A	1996-09-27
JPH0254572A	1990-02-23
JPS58220464A	1983-12-22

Mitsumasa Tokuwaka

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