Title:
2レベルの分岐予測キャッシュによる分岐予測
Document Type and Number:
Japanese Patent JP3798404
Kind Code:
B2
Abstract:
A processor is configured with a first level branch prediction cache configured to store branch prediction information corresponding to a group of instructions. In addition, a second level branch prediction cache is utilized to store branch prediction information which is evicted from the first level cache. The second level branch prediction cache is configured to store only a subset of the information which is evicted from the first level cache. Branch prediction information which is evicted from the first level cache and not stored in the second level cache is discarded. Upon a miss in the first level cache, a determination is made as to whether the second level cache contains branch prediction information corresponding to the miss. If corresponding branch prediction information is detected in the second level cache, the detected branch prediction information is used to rebuild complete branch prediction information.
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Inventors:
Gerald Dee. Zlasky
James S. Roberts
James S. Roberts
Application Number:
JP2003521935A
Publication Date:
July 19, 2006
Filing Date:
June 27, 2002
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F9/38; G06F12/08
Domestic Patent References:
| JP2001249806A | ||||
| JP2001521241A | ||||
| JP7200399A | ||||
| JP5120013A | ||||
| JP363726A | ||||
| JP1239638A |
Foreign References:
| WO1999022293A1 |
Other References:
Chris H. Perleberg 外1名,"Branch Target Buffer Design and Optimization",IEEE Transaction on Computers,米国,1993年 4月,第42巻,第4号,p.396-412
Attorney, Agent or Firm:
Masatake Suzuki
Ryota Sano
Yoshito Muramatsu
Ryota Sano
Yoshito Muramatsu