Title:
複数のメモリアドレスを格納および処理するための方法およびシステム
Document Type and Number:
Japanese Patent JP3841442
Kind Code:
B2
Abstract:
A packetized dynamic random access memory ("DRAM") receives command packets each of which contain a plurality of command words. One of the command words in each command packet includes a column address. Each of the command words, including the column address, is stored in one of a plurality of storage units so that a plurality of column addresses may be simultaneously stored in the storage units. The column addresses are individually coupled from respective storage units to a common column address bus which includes an address latch. The column address bus drives a column address processing circuit, such as a column address decoder. Also included is an adder that allows the DRAM to operate in a burst mode. In response to receiving an increment signal, the adder increments the column address at the output of the column address bus and applies the incremented address to the input of the column address bus.
Inventors:
Manning, Troy A.
Application Number:
JP50324799A
Publication Date:
November 01, 2006
Filing Date:
June 12, 1998
Export Citation:
Assignee:
MICRON TECHNOLOGY,INC.
International Classes:
G11C11/407; G11C5/06; G11C7/10; G11C11/401
Domestic Patent References:
| JP4243085A | ||||
| JP7334996A | ||||
| JP6119236A | ||||
| JP5002876A | ||||
| JP8249877A |
Foreign References:
| WO1997014289A1 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita
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