Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP3887171
Kind Code:
B2
Abstract:
When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circuits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.

Inventors:
Satoshi Tanaka
Shigetaka Takagi
Nobuo Fujii
Application Number:
JP2000595422A
Publication Date:
February 28, 2007
Filing Date:
January 17, 2000
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Renesas Technology Corp.
International Classes:
H03F3/45; H03H11/04
Domestic Patent References:
JPH10323439A1998-12-08
JPH08139534A1996-05-31
JPH098570A1997-01-10
JPH07283690A1995-10-27
JPH1041782A1998-02-13
JPH10322143A1998-12-04
JPH1117466A1999-01-22
Attorney, Agent or Firm:
Katsuo Ogawa