Title:
半導体ウエーハ及び半導体ウエーハの加工方法
Document Type and Number:
Japanese Patent JP3932097
Kind Code:
B2
Abstract:
In order to improve the productivity or production yield of chips in the process for device fabrication, the present invention provides a wafer or an apparatus of process for fabricating semiconductor devices having the backside of the wafer or the surface of a wafer holding means adjusted so as to have a distribution in contact surface density between the surface of the wafer holding means and the backside of the wafer when the semiconductor wafer is held on the wafer holding means in the process for fabricating devices.
Inventors:
Kiyoshi Izumi
Tadahiro Kato
Shigeyoshi Narazu
Tadahiro Kato
Shigeyoshi Narazu
Application Number:
JP2001581330A
Publication Date:
June 20, 2007
Filing Date:
April 26, 2001
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
H01L21/02; H01L21/304; H01L21/60; H01L21/68; H01L21/687
Attorney, Agent or Firm:
Masahisa Takahashi
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