Title:
遅延時間演算プログラム、および遅延時間演算装置
Document Type and Number:
Japanese Patent JP3935929
Kind Code:
B2
Abstract:
A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of a DMAG value is extracted (S5). The minimum value or/and the maximum delay time is/are calculated for every circuit cell by multiplying the standard delay time to the extracted DMAG value (S6). The above processing is performed for all the circuit cells constituting the logic circuit ((S7): NO), and the data set of the minimum or/and maximum delay time in the use condition range of the logic circuit is/are acquired for every circuit cell (S8). When the delay time characteristic of the circuit cell is nonlinear, the delay time serving as the minimum or/and the maximum for every circuit cell can be freely selected in the range of the circuit use condition unlike the case where the delay time is calculated by uniformly assigning the same use condition to all circuit cells.
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Inventors:
Atsushi Kizen
Application Number:
JP2005508795A
Publication Date:
June 27, 2007
Filing Date:
September 05, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Domestic Patent References:
| JP9311877A | ||||
| JP2000040098A | ||||
| JP2000195960A | ||||
| JP63150766A |
Other References:
井上雅夫,外2名,スタンダードセル遅延パラメータ抽出システム,情報処理学会全国大会講演論文集,情報処理学会,1986年10月,Vol.33,No.3,p.2251-2252
豊田徹,外5名,VLSI遅延ライブラリ作成支援システム,情報処理学会研究報告,社団法人情報処理学会,1991年 7月12日,Vol.91,No.58(91-DA-58),p.1-8
豊田徹,外5名,VLSI遅延ライブラリ作成支援システム,情報処理学会研究報告,社団法人情報処理学会,1991年 7月12日,Vol.91,No.58(91-DA-58),p.1-8
Attorney, Agent or Firm:
Patent Business Corporation Cosmos Patent Office