Title:
分散コンピュ-タシステムのオペレーション方法
Document Type and Number:
Japanese Patent JP3973560
Kind Code:
B2
Abstract:
A method for operation of a distributed computer system (SYS) comprising network nodes (NKN, NK 1 -NK 6 ), each of which has at least one node controller (STR, ST 1 -ST 6 ) and one communication controller (KK 1 -KK 6 ), the communication controllers (KKK, KK 1 -KK 6 ) being connected to each other via at least one communication channel (BUS), and provision being made between the communication controller (KK 1 -KK 6 ) and the node controller (STR, ST 1 -ST 6 ) of a network node (NKN, NK 1 -NK 6 ) for a fault tolerance layer (FTS, FT 1 -FT 6 ) that is set up to receive messages exchanged between the network nodes (NKN, NK 1 -NK 6 ), the fault tolerance layer (FTS, FT 1 -FT 6 ) deciding, based on information received pertaining to the status of at least one network node(NKN, NK 1 -NK 6 ), about the functioning of the at least one network node (NK 1 -NK 6 ) via a coordination procedure, and the coordination result being made available as an output signal (ASS, AS 1 -AS 6 ), the at least one network node (NKN, NK 1 -NK 6 ) being triggered as a function of the output signal (ASS, AS 1 -AS 6 ).
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Inventors:
Stefan Poledona
Application Number:
JP2002578131A
Publication Date:
September 12, 2007
Filing Date:
March 27, 2002
Export Citation:
Assignee:
TE Tech Computer Technique AG
International Classes:
G06F11/20; G06F11/00; G06F11/18
Domestic Patent References:
| JP2000322101A |
Other References:
Transparent Redundancy in the Time-Triggered Architecture,2000IEEE INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEM AND NETWORKS,米国,IEEE COMP.SOC,2000年,P5-13
Attorney, Agent or Firm:
Goji Kubotani