データ送受信回路 - Advantest Corporation

Title:

データ送受信回路

Document Type and Number:

Japanese Patent JP3989628

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To suppress power consumption of a line termination resistor of the data transmission reception circuit mounted on a small-sized computer or the like. SOLUTION: The data transmission reception circuit comprises a data transmission reception circuit with low power consumption and a data transmission reception circuit 2 placed to the other end. In the data transmission reception circuit 1, a receiver 3 and a tri-state driver 4 connect with one end of a data line L1 and a driver 5 that transmits an enable signal connects with an end of a control line L2. A resistor R4, whose resistance is nearly equal to a characteristic impedance Zo of the line L2, is connected with the other end of L2 in the transmission reception circuit 2. A receiver 6 connects with the other end of the line L1 and a tri-state transmission circuit 11 connects with the other end of the line L1 via a resistor R1 whose resistance is nearly equal to the characteristic impedance Z of the line L1, a DC power supply connects with the other end of the line L1 via a tri-state buffer 9 and a resistor R2, and a common potential point connects with the other end of the line L1 via a tri-state buffer 10 and a resistor R3. A parallel-combined resistance of the resistor R2, R3 is selected nearly equal to the impedance Zo.

Inventors:

Kumaki Norio

Application Number:

JP18256398A

Publication Date:

October 10, 2007

Filing Date:

June 29, 1998

Export Citation:

Click for automatic bibliography generation Help