Title:
半導体チップおよび半導体チップのテスト方法
Document Type and Number:
Japanese Patent JP3998647
Kind Code:
B2
Abstract:
A semiconductor chip comprise a semiconductor substrate; circuit elements formed on a surface of the semiconductor substrate; a wiring layer including wiring electrically connected to the circuit elements; an intermediate insulation layer provided between the wiring layer and the semiconductor substrate; a first guard ring provided in the intermediate insulation layer so as to surround a periphery of the circuit elements; a plurality of capacitor electrodes provided at intervals in the intermediate insulation layer and located between the first guard ring and the circuit elements or outside the first guard ring; and a plurality of capacitor pads electrically connected to each of the capacitor electrodes, respectively.
Inventors:
Oki Chi Fu
Application Number:
JP2004034624A
Publication Date:
October 31, 2007
Filing Date:
February 12, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/28; G01R31/26; H01L21/66; H01L21/822; H01L27/04; H01L29/76
Domestic Patent References:
| JP2004214626A | ||||
| JP63029942A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Akaoka Akira