Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP4003888
Kind Code:
B2
Abstract:
On a silicon substrate 1 is provided a silicon oxide film 2, on which a polycrystalline silicon film 3 is formed by a low pressure CVD method at a monosilane partial pressure of no more than 10 Pa and a film formation temperature of no lower than 600° C. The polycrystalline silicon film is doped with an impurity such as phosphorus in a concentration of 1x1020 atoms/cm3 to 1x1021 atoms/cm3 to form a phosphosilicate glass film 6, and after removing it, the polycrystalline silicon film is thermally oxidized in an oxidative atmosphere to form a dielectric film 5 on the surface. A polycrystalline silicon film 4 is formed on the dielectric film 5, which is treated as the oriented polycrystalline silicon film 3a to form an oriented polycrystalline silicon film 4a. The oriented polycrystalline silicon film 4a as an upper electrode and the oriented polycrystalline silicon film 3a as a lower electrode are wired to obtain a semiconductor device having a capacitor. Further, a thin film transistor of a high dielectric strength can be produced in a short time on the polycrystalline silicon which is oriented in a short time.
Inventors:
Yoshihiro Ogusa
Tatsuya Yamauchi
Tatsuya Yamauchi
Application Number:
JP50031397A
Publication Date:
November 07, 2007
Filing Date:
June 06, 1996
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H01L21/822; H01L21/02; H01L21/205; H01L21/28; H01L21/336; H01L27/04; H01L29/04; H01L29/786
Domestic Patent References:
| JP2081421A | ||||
| JP7072512A | ||||
| JP6260303A | ||||
| JP7038112A | ||||
| JP5055510A | ||||
| JP4233758A | ||||
| JP4139728A | ||||
| JP5009090A | ||||
| JP4233270A |
Attorney, Agent or Firm:
Yoshikazu Tani