Title:
ラッチアップ耐性のための高保持電流を有する静電放電保護構造
Document Type and Number:
Japanese Patent JP4005920
Kind Code:
B2
Abstract:
An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
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Inventors:
Margens, Marcus
Russ, christian
John Armor
Bellarge, Cohen
Hoswiak, Philip
Russ, christian
John Armor
Bellarge, Cohen
Hoswiak, Philip
Application Number:
JP2002574200A
Publication Date:
November 14, 2007
Filing Date:
March 15, 2002
Export Citation:
Assignee:
Sarnoff Corporation
Sarnoff Europe BV
Sarnoff Europe BV
International Classes:
H01L21/822; H01L29/74; H01L21/8238; H01L23/62; H01L27/02; H01L27/04; H01L27/06; H01L27/092; H02H9/00
Domestic Patent References:
| JP5315552A | ||||
| JP7506216A |
Attorney, Agent or Firm:
Yuichi Yamada
Yasuhito Suzuki
Katsuyuki Ninomiya
Yasuhito Suzuki
Katsuyuki Ninomiya