Title:
IC設計用の垂直スタック型コプレーナ伝送線路構造
Document Type and Number:
Japanese Patent JP4009281
Kind Code:
B2
Abstract:
A vertically stacked coplanar transmission line structure for an IC (integrated circuit) is provided which has superior loss and reflection characteristics relative to conventional on-chip transmission line designs. A simple embodiment of the vertically stacked coplanar transmission line structure comprises a micro-strip pair of first and second vertically stacked coplanar conductors, each comprising a metal layer, a next metal layer down, and an intermediate connecting via layer in between the metal layer and the next metal layer down.
Inventors:
Raminder Pal Singh
Yuri V. Tretyakov
Kunal Vade
Wayne H. Woods Jr.
Yuri V. Tretyakov
Kunal Vade
Wayne H. Woods Jr.
Application Number:
JP2004266306A
Publication Date:
November 14, 2007
Filing Date:
September 14, 2004
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L27/04; H01P3/02; H01L21/82; H01L21/822; H01L23/522; H01L23/66
Domestic Patent References:
| JP2000059113A | ||||
| JP2002084107A | ||||
| JP2004328123A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno