Title:
相互接続構造及びこれの製造方法
Document Type and Number:
Japanese Patent JP4012513
Kind Code:
B2
Abstract:
A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
Inventors:
Magal Lane, John, Harold
Petraka, Kevin, Sean
Persosaman, Sampath
Sam Busetti, Carlos, Jean
Borant, Richard, Paul
Walker, George, Frederick
Petraka, Kevin, Sean
Persosaman, Sampath
Sam Busetti, Carlos, Jean
Borant, Richard, Paul
Walker, George, Frederick
Application Number:
JP2003560962A
Publication Date:
November 21, 2007
Filing Date:
December 19, 2002
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/60; H01L21/00; H01L23/485; H01L23/498; H05K1/11; H05K3/34; H05K1/03; H05K3/38
Domestic Patent References:
| JP2001298037A | ||||
| JP2000164621A | ||||
| JP2000306914A | ||||
| JP2000091339A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno