Title:
フォーマット変換回路
Document Type and Number:
Japanese Patent JP4030055
Kind Code:
B2
Abstract:
A format conversion circuit 100 includes a FIFO memory 101 for writing and reading video data VD in synchronization with a sampling clock CK, a header generation circuit 102 for generating an MPEG2-TS packet header, and a synchronous timing detection circuit 103 for detecting a horizontal synchronizing signal for the video data VD. The format conversion circuit 100 also includes a counter 104 which counts the number of bytes of packet header and the number of bytes of video data VD, and a switch 105 which selects the packet header until the counted number of bytes reaches four bytes, and then selects the video data read out of the FIFO memory 101.
Inventors:
Masahiro Murakami
Hiroaki Kubo
Hiroaki Kubo
Application Number:
JP2002342268A
Publication Date:
January 09, 2008
Filing Date:
November 26, 2002
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H04N5/92; H04N5/44; H04N7/173; H04N19/00; H04N19/423; H04N19/426; H04N19/85; H04N21/438; H04N21/4402; H04N5/46
Domestic Patent References:
| JP2001251266A | ||||
| JP2000165445A |
Foreign References:
| WO1998043423A1 |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno