Title:
基板及びその製造方法
Document Type and Number:
Japanese Patent JP4030285
Kind Code:
B2
Abstract:
It is an object to provide a method of efficiently manufacturing a double-sided circuit board having a metallic via hole which can suitably be used as a submount for mounting a semiconductor device, that is, a substrate in which the electrical contact of a metallic via hole and a circuit pattern is excellent and an element can easily be bonded and positioned. In a ceramic substrate having a via hole filled with a conductive material, a ceramic portion of at least one of faces of the ceramic substrate has a surface roughness of Ra ≤ 0.8 mu m, a substrate in which the conductive material filled in the via hole present on at least one of the faces is protruded from a surface of the face with a height of 0.3 to 5.0 mu m is used as a material substrate and a conductive layer is formed on the surface, and subsequently, the conductive layer is patterned and a solder film pattern for element mounting is formed based on a position of a convex portion of the conductive layer which results from the via hole present on an underlaid portion of the conductive layer.
Inventors:
Yamamoto Reo
Kamiyama Mihide
Kamiyama Mihide
Application Number:
JP2001312516A
Publication Date:
January 09, 2008
Filing Date:
October 10, 2001
Export Citation:
Assignee:
Tokuyama Corporation
International Classes:
H01L23/13; H01L23/15; H01L23/36; H01L23/498; H01S5/022; H05K1/02; H05K1/11; H05K3/06; H05K3/14; H05K1/03; H05K3/00; H05K3/24; H05K3/40
Domestic Patent References:
| JP11251700A | ||||
| JP2001244626A | ||||
| JP2001057471A |