Title:
実装構造体の製造方法および実装構造体
Document Type and Number:
Japanese Patent JP4036555
Kind Code:
B2
Abstract:
A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
Inventors:
Kazuyoshi Amami
Shiraishi Tsukasa
Yoshihiro Bessho
Shiraishi Tsukasa
Yoshihiro Bessho
Application Number:
JP751999A
Publication Date:
January 23, 2008
Filing Date:
January 14, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/60; H01L21/56; H05K3/30; H05K3/32
Domestic Patent References:
| JP2000068321A | ||||
| JP8250543A | ||||
| JP9181122A |
Attorney, Agent or Firm:
Kazuhide Okada