Title:
メモリアクセス方式
Document Type and Number:
Japanese Patent JP4042088
Kind Code:
B2
Abstract:
The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
Inventors:
Yasuhiro Nakatsuka
Tetsuya Shimomura
Castle study
Yuichiro Morita
Takashi Hotta
Kazushige Yamagishi
Yutaka Okada
Tetsuya Shimomura
Castle study
Yuichiro Morita
Takashi Hotta
Kazushige Yamagishi
Yutaka Okada
Application Number:
JP2000254986A
Publication Date:
February 06, 2008
Filing Date:
August 25, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F13/16; G06F3/153; G06F12/00; G06F12/04; G09G5/39
Domestic Patent References:
| JP11296154A | ||||
| JP200082009A | ||||
| JP2001265303A |
Other References:
城学他,個人情報機器に適したグラフィックスプロセッサQ2SDの開発,1999年電子情報通信学会総合大会講演論文集,社団法人電子情報通信学会,1999年 3月 8日,情報・システム[2],第163頁,D-11-163
Attorney, Agent or Firm:
Shigeru Sasaoka