Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4043855
Kind Code:
B2
Abstract:
A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.
Inventors:
Kayoko Saito
Kusunoki
Hiroyasu Ishizuka
Shinichiro Masuda
Kusunoki
Hiroyasu Ishizuka
Shinichiro Masuda
Application Number:
JP2002168680A
Publication Date:
February 06, 2008
Filing Date:
June 10, 2002
Export Citation:
Assignee:
株式会社日立製作所
株式会社日立超エル・エス・アイ・システムズ
株式会社日立超エル・エス・アイ・システムズ
International Classes:
H01L21/822; H01L27/04; G11C5/14; G11C11/417; H01L21/8238; H01L27/02; H01L27/092; H01L27/105; H01L27/11; H03K5/007; H03K5/08; H03K19/003
Domestic Patent References:
| JP2000155620A | ||||
| JP2000077608A | ||||
| JP5053669A | ||||
| JP2002305245A | ||||
| JP9148527A |
Attorney, Agent or Firm:
Shizuyo Tamamura