Title:
シリアルフラッシュメモリにおけるXIPのための優先順位に基づくフラッシュメモリ制御装置及びこれを用いたメモリ管理方法、これによるフラッシュメモリチップ
Document Type and Number:
Japanese Patent JP4044067
Kind Code:
B2
Abstract:
A priority-based flash memory control apparatus (500) for XIP in a serial flash memory (100), a memory management method using the same, and a memory chip thereof. Efficient memory management is provided by assigning priorities to respective pages of a serial flash memory (100) and storing the pages retrieved from the serial flash memory (100) in a system memory (700) or cache memory (523) according to their priority. A memory management method using the flash memory control apparatus (500) according to the present invention includes, if a request for reading data at a given logical address is received from a main control unit (300), searching for the data at the corresponding logical address by referring to a predetermined address translation table; and reading the data at the corresponding logical address from a system memory (700) or a cache memory (523) and transmitting the read data to the main control unit (300), depending on the results of the search.
Inventors:
Park Iku
Application Number:
JP2004106979A
Publication Date:
February 06, 2008
Filing Date:
March 31, 2004
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F12/12; G06F9/445; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G11C16/02; G11C16/26
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Other References:
Home Toys Inc.,One Chip That Does It All,2001年12月,URL:http://hometoys.com/htinews/dec01/articles/msystems/msystems.htm
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe