Title:
信号処理回路
Document Type and Number:
Japanese Patent JP4045672
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To generate a clock with a frequency in compliance with an application side and to obtain data that can be processed at the application side by converting a frequency of a system clock into a frequency in compliance with the specification of the application side so as to eliminate the need for separate provision of a read clock generating circuit at the outside of the circuit. SOLUTION: A reception pre-processing circuit 8 receives a communication packet transferred via a link core 101 and stores a source packet header and data to an FIFO 110. A reception post-processing circuit 109 receives a system clock SCLK fed from the link core 101 and converts its frequency into a frequency in compliance with the specification of an application side. Then packet data stored in the FIFO 110 are read based on the clock whose frequency is converted and the data are outputted to an MPEG transporter 40 as MPEG transport stream data via an application interface circuit 103.
Inventors:
Sadaharu Sato
Application Number:
JP30609198A
Publication Date:
February 13, 2008
Filing Date:
October 27, 1998
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F13/38; H04L29/10; G06F1/12; H04L12/70
Domestic Patent References:
| JP8242255A | ||||
| JP10283289A | ||||
| JP10285284A |
Attorney, Agent or Firm:
Takahisa Sato