Title:
受信回路
Document Type and Number:
Japanese Patent JP4046987
Kind Code:
B2
Abstract:
A receiving circuit including an amplifier for generating a receiving voltage signal, a comparator for generating a binary signal from the receiving voltage signal, and a logic maintaining circuit for receiving the binary signal and maintaining the binary signal at a shifted level for a predetermined period after the level of the binary signal is shifted. The logic maintaining circuit prevents noise pulses from appearing in a receiving signal.
Inventors:
Nishizono Kazunori
Application Number:
JP2001361298A
Publication Date:
February 13, 2008
Filing Date:
November 27, 2001
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03F3/08; H03G11/04; H03F1/26; H03F1/34; H03F3/45; H03K5/08; H03K5/1252; H04B10/116; H04B10/40; H04B10/50; H04B10/60
Domestic Patent References:
| JP11298033A | ||||
| JP10294622A | ||||
| JP2000315923A | ||||
| JP5034714U | ||||
| JP57207456A |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda