Title:
入力回路
Document Type and Number:
Japanese Patent JP4047178
Kind Code:
B2
Abstract:
An input circuit for preventing the application of a voltage exceeding a transistor withstand voltage when the input circuit is switched to a standby state. The input circuit includes a first differential amplification circuit powered by a first power supply to amplify a first input signal and generate a second input signal. A level shift circuit is powered by the first power supply to generate a shifted input signal from the second input signal. A second differential amplification circuit is powered by a second power supply to amplify the shifted input signal and generate an amplified signal. A current control circuit selectively switches the input circuit between activated and standby states. A first circuit charges or discharges the level shift circuit so that voltage of the shifted input signal is less than or equal to voltage of the second power supply when switched to the standby state.
Inventors:
Tomohiko Furudo
Application Number:
JP2003000552A
Publication Date:
February 13, 2008
Filing Date:
January 06, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K19/0175; H03F1/52; H03F3/45; H03K5/22; H03K5/24; H03K19/00; H03K19/003; H03K19/0185
Domestic Patent References:
| JP10084274A | ||||
| JP9294062A | ||||
| JP2000183723A | ||||
| JP7142988A | ||||
| JP5160709A |
Foreign References:
| WO2002047063A1 |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda