Title:
電源配線設計方法、電源配線設計装置、記録媒体、及びプログラム
Document Type and Number:
Japanese Patent JP4053767
Kind Code:
B2
Abstract:
A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.
Inventors:
Inui Masyu
Takashi Kurihara
Takashi Kurihara
Application Number:
JP2001374364A
Publication Date:
February 27, 2008
Filing Date:
December 07, 2001
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
| JP1241843A | ||||
| JP58166743A |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda