Title:
メモリ制御回路、DMA要求ブロック及びメモリアクセスシステム
Document Type and Number:
Japanese Patent JP4054598
Kind Code:
B2
Abstract:
A DMA controller arbitrates and selects a DMA control information signal received from at least one of a plurality of DMA request blocks and accesses an SDRAM on the basis of the selected DMA control information signal. In the DMA controller, an SDRAM controller detects using a detector the number of possible sequential accesses on the basis of a DMA start address signal, compares using a comparator this number of possible sequential accesses with the burst DMA request number designated by a BSTNUM signal, selects not larger one of the two numbers, and sets the number of sequential DMAs to be actually executed to the selected number. Accordingly, with a simple configuration, sequential access is made possible starting from an arbitrary address.
Inventors:
Akira Kuronuma
Toru Nakayama
Takuji Katsu
Sohei Tanaka
Masafumi Wataya
Toru Nakayama
Takuji Katsu
Sohei Tanaka
Masafumi Wataya
Application Number:
JP2002123811A
Publication Date:
February 27, 2008
Filing Date:
April 25, 2002
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F12/02; G06F12/00; G06F13/28
Domestic Patent References:
| JP2000227897A | ||||
| JP8147238A | ||||
| JP2000132497A |
Attorney, Agent or Firm:
Keizo Nishiyama
Yuichi Uchio
Yuichi Uchio