Title:
同期マルチ出力デジタルクロックマネージャ
Document Type and Number:
Japanese Patent JP4056388
Kind Code:
B2
Abstract:
A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.
Inventors:
Rogue, John Di
Percy, Andrew Kay
Getting, F. Erich
Percy, Andrew Kay
Getting, F. Erich
Application Number:
JP2002533473A
Publication Date:
March 05, 2008
Filing Date:
October 05, 2001
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H04L7/00; G06F1/06; G06F1/10; H03L7/07; H03L7/081
Domestic Patent References:
| JP4505539A | ||||
| JP7202655A | ||||
| JP2002409A | ||||
| JP9148919A |
Foreign References:
| WO1999067882A1 | ||||
| US5805003 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai