Title:
配線基板及びその製造方法、電子部品、回路基板並びに電子機器
Document Type and Number:
Japanese Patent JP4058607
Kind Code:
B2
Abstract:
An interconnect substrate including a first substrate on which a first interconnect pattern is formed, having a mounting region for an electronic chip; and a second substrate on which a second interconnect pattern electrically connected to the first interconnect pattern is formed. The second substrate includes a region to which at least a part of the first substrate is adhered, and a mounting region for an electronic chip.
Inventors:
Nobuaki Hashimoto
Application Number:
JP2001519491A
Publication Date:
March 12, 2008
Filing Date:
August 11, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L23/52; H01L23/538; H01L25/065; H01L25/07; H01L25/18; H05K3/00; H05K3/40; H05K1/14; H05K1/18; H05K3/38; H05K3/46
Domestic Patent References:
| JP6058941B2 | ||||
| JP62158397A | ||||
| JP7273448A | ||||
| JP11135715A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Mitsue Obuchi