Title:
メモリ回路及びデータ消去及び書き込み方法
Document Type and Number:
Japanese Patent JP4059065
Kind Code:
B2
Abstract:
To reduce power consumption in deleting and writing data in a memory circuit of EEPROM.
Reduction of power consumption is carried out by gently performing charging/discharging in deleting of data and in writing data by connecting a power clock from a potential recycling power source which performs charging/discharging intermittently, to a word line and a bit line in a memory circuit.
COPYRIGHT: (C)2004,JPO
Inventors:
Shunji Nakata
Application Number:
JP2002331275A
Publication Date:
March 12, 2008
Filing Date:
November 14, 2002
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G11C16/04; G11C16/06; G11C16/02; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP10283784A | ||||
| JP2000077994A |
Attorney, Agent or Firm:
Tadahiko Ito