電子装置の製造方法

Japanese Patent JP4060882

B2

A method of manufacturing a device whereby a layer structure with semiconductor elements and conductor tracks is formed on a first side of a semiconductor wafer which is provided with a layer of semiconductor material disposed on an insulating layer. Then the semiconductor wafer is fastened with said first side to a support wafer by means of a glue layer, the support wafer being provided with a metallization. Material is then removed from the semiconductor wafer from the other, second side thereof until the insulating layer is exposed. Contact windows are provided in the insulating layer from the first side of the semiconductor wafer before the latter is refastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed. Furthermore, openings are formed in the layer structure and in the flue layer at the areas of the contact windows, which openings extend down to the metallization on the support wafer, after which the contact windows and the openings formed are provided with conductive elements.

Mars Henrix Hode Fridas Rafael
Deckle ronald
Van der zen maria henryka wilhelmina antonia

JP53391096A

March 12, 2008

April 18, 1996

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Koninklijke Philips Electronics N.V.

G02F1/136; H01L21/336; G02F1/1368; H01L21/02; H01L21/58; H01L21/60; H01L21/768; H01L21/77; H01L23/498; H01L23/522; H01L27/12; H01L29/786; H02M3/155; H02M3/28

JP4255268A

Kenji Sugimura
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada

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