Title:
MOSトランジスタ、DRAMセル構成体、およびMOSトランジスタの製造方法
Document Type and Number:
Japanese Patent JP4064107
Kind Code:
B2
Abstract:
A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
Inventors:
Kraut Schneider, Wolfgang
Chiller, til
Villa, joseph
Chiller, til
Villa, joseph
Application Number:
JP2001506607A
Publication Date:
March 19, 2008
Filing Date:
May 29, 2000
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L29/78; H01L21/336; H01L21/8234; H01L21/8242; H01L27/088; H01L27/108; H01L29/41; H01L29/423; H01L29/49; H01L29/786
Domestic Patent References:
| JP6085262A | ||||
| JP63241967A |
Foreign References:
| US5907170 |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko