Title:
OPCを用いたパターン寸法の補正方法及び検証方法、マスクの作成方法及び半導体装置の製造方法、並びに該補正方法を実行するシステム及びプログラム
Document Type and Number:
Japanese Patent JP4068531
Kind Code:
B2
Abstract:
A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.
Inventors:
Toshiya Kotani
Nojima Shigeki
Nojima Shigeki
Application Number:
JP2003296238A
Publication Date:
March 26, 2008
Filing Date:
August 20, 2003
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G03F1/36; G03F1/68; G03F1/70; G06F17/50; H01L21/00; H01L21/027
Domestic Patent References:
| JP2003167323A | ||||
| JP2002311562A | ||||
| JP2000232057A |
Foreign References:
| WO2001065315A2 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki