Title:
ヘテロ接合型半導体装置
Document Type and Number:
Japanese Patent JP4075218
Kind Code:
B2
Inventors:
Tomoyoshi Kushida
Application Number:
JP17006099A
Publication Date:
April 16, 2008
Filing Date:
June 16, 1999
Export Citation:
Assignee:
TOYOTA JIDOSHA KABUSHIKI KAISHA
International Classes:
H01L29/861; H01L29/12; H01L29/739; H01L29/78
Domestic Patent References:
| JP4234136A | ||||
| JP9213711A | ||||
| JP59184516A | ||||
| JP62033481A | ||||
| JP9283797A | ||||
| JP2000511003A | ||||
| JP2001525614A |
Foreign References:
| WO1998042029A1 |
Other References:
Srikanth B. Samavedam and E. A. Fitzgerald,Novel dislocation structure and surface morphology effects in relaxed Ge/Si-Ge(graded)/Si Structures,Journal of Applied Physics,米国,American Institute of Physics,1997年 4月 1日,Vol.81, No.7,pp.3108-3116
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida