Title:
マルチ-ビットデータを貯蔵するための半導体メモリ装置
Document Type and Number:
Japanese Patent JP4083908
Kind Code:
B2
Abstract:
Disclosed herein is an integrated circuit memory device which includes a memory cell arranged at an intersection of a word line and a bit line and a bit line precharge circuit for providing the bit line with a predetermined current during respective bit line precharge and sensing periods of time of a data reading operation in response to a bit line precharge signal. The integrated circuit memory device further includes a bit line pass transistor which has a gate and connected between the bit line precharge circuit and the bit line and which transfers the current from the bit line precharge circuit onto the bit line. Furthermore, the device includes a bias voltage supplying circuit which supplies the gate of the bit line pass transistor with a bias voltage during the data reading operation. In this embodiment, the bias voltage supplying circuit makes a voltage on the gate of the bit line pass transistor become discharged under the bias voltage during a bit line discharge period of time of the data reading operation.
Inventors:
Zhang Cheol Male
Application Number:
JP37259398A
Publication Date:
April 30, 2008
Filing Date:
December 28, 1998
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G11C16/02; G11C11/34; G11C16/06; G11C11/56
Domestic Patent References:
| JP10283788A | ||||
| JP9204788A | ||||
| JP2257495A | ||||
| JP8321195A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe