Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP4091265
Kind Code:
B2
Abstract:
A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1x1017 cm-3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
Inventors:
Yuichiro Mitani
Hideki Satake
Hideki Satake
Application Number:
JP2001100399A
Publication Date:
May 28, 2008
Filing Date:
March 30, 2001
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8247; H01L29/78; H01L21/28; H01L21/30; H01L21/316; H01L21/318; H01L27/115; H01L29/51; H01L29/788; H01L29/792
Domestic Patent References:
| JP10223628A | ||||
| JP11238702A | ||||
| JP11274489A | ||||
| JP10303424A | ||||
| JP2000077621A | ||||
| JP2000208526A | ||||
| JP8507175A | ||||
| JP2000503479A |
Other References:
Yuichiro Mitani, Hideki Satake, Hitoshi Itoh and Akira Toriumi,Highly Reliable Gate Oxide under Fowler-Nordheim Electron Injection by Deuterium Pyrogenic Oxidation,International Electron Devices Meeting 2000. Technical Digest. IEDM,2000年12月10日,pp.343-346
N.S. Saks and R. W. Rendell,The time-dependence of post-irradiation interface trap build-up in deuterium-annealed oxides,Nuclear Science, IEEE Transactions on,1992年12月,Vol.39, Issue 6, Part 1-2,pp.2220-2229
N.S. Saks and R. W. Rendell,The time-dependence of post-irradiation interface trap build-up in deuterium-annealed oxides,Nuclear Science, IEEE Transactions on,1992年12月,Vol.39, Issue 6, Part 1-2,pp.2220-2229
Attorney, Agent or Firm:
Hiroshi Horiguchi