Title:
半導体装置
Document Type and Number:
Japanese Patent JP4091838
Kind Code:
B2
Abstract:
The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.
Inventors:
Yoshiharu Kato
Satoru Kawamoto
Fumihiko Taniguchi
Tetsuya Hiraoka
Akira Takashima
Satoru Kawamoto
Fumihiko Taniguchi
Tetsuya Hiraoka
Akira Takashima
Application Number:
JP2002536861A
Publication Date:
May 28, 2008
Filing Date:
March 30, 2001
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L25/065; H01L21/66; H01L23/48; H01L25/07; H01L25/18
Domestic Patent References:
| JP8213545A | ||||
| JP10079466A | ||||
| JP60018934A | ||||
| JP62101048A | ||||
| JP11031781A | ||||
| JP11168185A | ||||
| JP2122559A |
Foreign References:
| WO1999060618A1 |
Attorney, Agent or Firm:
Tadahiko Ito