Title:
集積化電子装置を封止するための端部構成体の製造方法及び対応する装置
Document Type and Number:
Japanese Patent JP4094713
Kind Code:
B2
Abstract:
A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30). In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).
Inventors:
Camilla Caregani
Carrara
Lorenzo Fractin
Carlo Riva
Carrara
Lorenzo Fractin
Carlo Riva
Application Number:
JP1849098A
Publication Date:
June 04, 2008
Filing Date:
January 30, 1998
Export Citation:
Assignee:
STMicroelectronics S.r.l.
International Classes:
H01L21/316; H01L23/28; H01L21/8247; H01L23/00; H01L23/31; H01L23/532; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP6188240A | ||||
| JP7122558A | ||||
| JP5082747A | ||||
| JP9186154A | ||||
| JP2062045A | ||||
| JP6232256A | ||||
| JP8037289A | ||||
| JP4279050A | ||||
| JP737839A |
Foreign References:
| US4760034 |
Attorney, Agent or Firm:
Masaaki Kobashi