Title:
半導体装置
Document Type and Number:
Japanese Patent JP4095827
Kind Code:
B2
Abstract:
In order to improve the mounting accuracy of QFN (Quad Flat Non-leaded package) having external connection terminals on a rear surface of the package, a semiconductor device and its manufacturing method are provided. In the QFN, notch sections are provided in the two diagonal corner portions on the front surface of the sealing body. Reference marks with a circular form are formed in the parts of the suspension leads exposed from the notch sections so that the positions of the reference marks can be optically detected from above the sealing body when mounting the QFN to the wiring board. The reference marks are formed by the etching to remove the parts of the metal plate that constitutes the suspension leads or by pressing the parts to punch them.
Inventors:
Fujio Ito
Suzuki Hiromichi
Suzuki Hiromichi
Application Number:
JP2002134952A
Publication Date:
June 04, 2008
Filing Date:
May 10, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L23/50; H01L21/48; H01L21/56; H01L23/31; H01L23/495; H01L23/52; H01L23/544
Domestic Patent References:
| JP6252326A | ||||
| JP7226475A | ||||
| JP63065660A | ||||
| JP2000091486A | ||||
| JP2001189402A |
Attorney, Agent or Firm:
Yamato Tsutsui